1. Field of the Invention
The present invention relates to a power supply circuit supplying a boosted voltage to a semiconductor device.
2. Description of the Related Art
Low voltage operations of a flash memory having a single power supply voltage are usually realized by supplying a voltage boosted to the required high voltage from the power supply voltage by a booster circuit on the chip.
For example, in a flash memory operating at a low power supply voltage of 3.3 V or less, a high voltage of, for example, 4 V to 5 V has to be input to the word lines to maintain the access speed during reading and writing.
Usually, a high voltage can be obtained by the method of using a bootstrap circuit or a booster circuit.
A bootstrap circuit uses a large capacitor to increase the voltage in synchronization with an address transition detection (ATD) pulse. The method of using a bootstrap circuit can only increase the power supply voltage V.sub.CC by 50% to 60% and therefore is not appropriate for power supply voltages of 3 V or less.
A booster circuit, for example, a charge pump type booster circuit, can output a boosted voltage higher than the power supply voltage by charging and discharging charge pumps formed by capacitors complementarily in response to a clock signal.
FIG. 1 is a circuit diagram of the configuration of a power supply circuit having a booster circuit according to the related art. In FIG. 1, reference number 10 denotes an oscillator, 20 a buffer, 30 a booster circuit, 40 a comparator, 50 a reference voltage generator, R.sub.L1 and R.sub.L2 resistors, ND.sub.0 a node, and T.sub.OUT an output terminal, respectively.
As shown in FIG. 1, a clock signal CLK is generated by the oscillator 10 and is input to the booster circuit 30 after being amplified by the buffer 20. A high voltage V.sub.OUT is generated by the booster circuit 30 using the clock signal CLK from the buffer 20 and is output to the output terminal T.sub.OUT.
The high voltage V.sub.OUT output to the output terminal T.sub.OUT is divided by the resistors R.sub.L1 and R.sub.L2 to generate a divided voltage V.sub.T of the node ND.sub.0 in response to the high voltage V.sub.OUT and is input to the comparator 40.
The comparator 40 is formed by, for example, a differential amplifier. The voltage V.sub.T of the node ND.sub.0 is input to one input T.sub.1 of the differential amplifier, while a reference voltage V.sub.ref generated by the reference voltage generator 50 is input to the other input T.sub.2 of the differential amplifier. The divided voltage V.sub.T of the node ND.sub.0 is compared with the reference voltage V.sub.ref by the comparator 40. An oscillation control signal OSS is generated for making the oscillator 10 operate when the voltage V.sub.T is lower than the reference voltage V.sub.ref and for stopping the oscillator 10 when the voltage V.sub.T is higher than the reference voltage V.sub.ref and is input to the oscillator 10.
For example, when the voltage V.sub.OUT of the output terminal T.sub.OUT falls, the level of the divided voltage V.sub.T of the node ND.sub.0 falls accordingly. When the voltage V.sub.T falls under the reference voltage V.sub.ref set by the reference voltage generator 50, the active state oscillation control signal OSS is generated by the comparator 40 and output to the oscillator 10. In response to this, for example, the frequency of the clock signal CLK generated by the oscillator 10 increases and the level of the output voltage V.sub.OUT of the booster circuit 30 is made higher.
On the other hand, when the voltage V.sub.OUT of the output terminal T.sub.OUT rises, the level of the divided voltage V.sub.T of the node ND.sub.0 rises accordingly. When the voltage V.sub.T becomes higher than the reference voltage V.sub.ref set by the reference voltage generator 50, the inactive state oscillation control signal OSS is generated by the comparator 40 and output to the oscillator 10. In response to this, for example, the frequency of the clock signal CLK generated by the oscillator 10 falls and the level of the output voltage V.sub.OUT of the booster circuit 30 is made lower.
In this way, the output voltage V.sub.OUT of the booster circuit 30 is fed back to the oscillator 10 and the frequency of the clock signal CLK from the oscillator 10 is controlled accordingly so as to hold the level of the boosted voltage V.sub.OUT generated by the booster circuit 30 at a constant level.
By using this kind of charge pump type booster circuit, a high voltage can be effectively generated even in the case of a relatively low power supply voltage, for example, one of not more than 3 V.
The power supply circuit of the related art explained above, however, has a disadvantage of consuming power even in the standby state. For example, in the power supply circuit shown in FIG. 1, power is consumed by the comparator 40, the reference voltage generator 50, etc. during standby. During standby, it is only necessary to compensate for the leakage currents in the transistors and diffusion layers, so only a small booster circuit need be operated. While only several hundred microamperes (.mu.A) of current is consumed at the most, there are applications in which there are problems even with this extent of current consumption.
For example, in a portable electronic device using batteries as a power source, it is desirable to lower the power consumption as much as possible during standby when the microprocessor has a clock function operating at a low voltage and low frequency.
Further, a flash memory is provided with a so-called "deep power down" mode where it stops all circuit operations so as to achieve lower power consumption. However, it takes time for returning to normal operation and it is difficult to handle low frequency operations as well.